UNIVERSITY OF CALIFORNIA, SAN DIEGO Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers

Figure 12: a) High-level block diagram of the segmented quantizer; b) quantization block details; c) signal processing model .. Figure 16: Estimated power spectra of a) the quantization noise sequences, and b) the running sums of the quantization noise sequences of the first-order ∆Σ modulator and the segmented quantizer presented in Section IV before and Ian Galton supervised the research which forms the basis of this paper. Andrea Pani-gada contributed to the theorem statements, and Elias Masry contributed to the structure of the proofs. Wang contributed to the design and implementation of the charge pump power reduction technique. xi xi VITA 1994 B. Delta-sigma fractional-N phase-locked loops are used to generate high quality radio-frequency signals for use in wireless applications. To reduce the phase noise inherent to these systems, a digital-to-analog converter is used to cancel the error introduced by the fractional division process, however matching between the digital-to-analog converter and the phase-locked loop circuitry place a limit on the amount of phase noise reduction that can be achieved. Furthermore, circuit non-linearity results xiii xiii in the appearance of spurious tones in the phase-locked loop output. This dissertation outlines a calibration technique, and a digital quantization technique that provide solutions to these two problems. The calibration technique results in improved phase noise performance by adjusting the digital-to-analog converter gain, and thus providing better matching between the phase-locked loop circuitry and digital-to-analog converter. The digital quantization technique results in no spurious tones when specified non-linearity is applied to the quantizer output sequence and error. The calibration technique was implemented in an integrated circuit, which achieves state-of-the-art performance when compared to currently published phase-locked loops and allows for all circuitry to be integrated onto a single chip. Chapter 1 presents the calibration technique, as well as a theoretical analysis of the stability. Chapter 2 presents details on the digital quantization technique, and a mathematical proof of the absence of spurious tones. In chapter 3, results from an implemented circuit are presented, which verify the behaviour of the technique presented in chapter 1. ABSTRACT Phase-noise canceling phase-locked loops (PLL) are sensitive to the matching between the phase noise canceling and PLL circuitry. Any mismatch places a limit on the quality of the phase noise cancellation, and as a result constrains the design of the PLL to accommodate the mismatch. This paper presents a calibration technique which estimates the mismatch, and adjusts the equivalent …